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embedded pentium ? processor with voltage reduction technology datasheet product features the embedded pentium ? processor is fully compatible with the entire installed base of applications for dos*, windows*, os/2*, and unix*, and all other software that runs on any earlier intel 8086 family product. the embedded pentium processors superscalar architecture can execute two instructions per clock cycle. branch prediction and separate caches also increase performance. separate code and data caches reduce cache conflicts while remaining software transparent. the embedded pentium processor with voltage reduction technology has 3.3 million transistors. it is built on intels advanced low-voltage bicmos silicon technology, and has full sl enhanced power management features, including system management mode (smm) and clock control. the additional sl enhanced features, 3.1 v core operation and 3.3 v i/o buffer operation, make the embedded pentium processor with voltage reduction technology ideal for embedded designs. n compatible with large software base ms-dos*, windows*, os/2*, unix* n 32-bit processor with 64-bit data bus n superscalar architecture two pipelined integer units are capable of two instructions/clock pipelined floating-point unit n separate code and data caches 8-kbyte code, 8-kbyte write-back data mesi cache protocol n advanced design features branch prediction virtual mode extensions n low-voltage bicmos silicon technology n 4-mbyte pages for increased tlb hit rate n ieee 1149.1 boundary scan n internal error detection features n sl enhanced power management features system management mode clock control n voltage reduction technology 3.1 v v cc for core supply 3.3 v v cc for i/o buffer supply n fractional bus operation 133-mhz core/66-mhz bus (icomp ? index 2.0 rating of 111) ? ? contact intel corporation for more information about icomp ? index 2.0 ratings. order number: 273203-001 november 1998
datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the pentium ? processor with voltage reduction technology may contain design defects or errors known as errata which may cause the product t o deviate from published specifications. current characterized errata are available on request. mpeg is an international standard for video compression/decompression promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various entities, including intel corporation. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1998 *third-party brands and names are the property of their respective owners.
datasheet 3 embedded pentium ? processor with voltage reduction technology contents 1.0 introduction .................................................................................................................. 7 2.0 architecture overview ............................................................................................. 7 2.1 pentium ? processor family architecture .............................................................. 8 3.0 packaging information ...........................................................................................10 3.1 differences from the pentium processor.............................................................10 3.2 pinout ..................................................................................................................11 3.2.1 pin cross reference ..............................................................................14 3.2.2 design notes..........................................................................................16 3.2.3 pin quick reference ..............................................................................16 3.2.4 pin reference tables.............................................................................22 3.2.5 pin grouping according to function.......................................................24 3.3 mechanical specifications ...................................................................................25 3.4 thermal specifications ........................................................................................26 3.4.1 measuring thermal values ....................................................................26 3.4.2 thermal equations .................................................................................27 4.0 electrical specifications ........................................................................................28 4.1 absolute maximum ratings.................................................................................28 4.2 dc specifications ................................................................................................28 4.2.1 power sequencing .................................................................................30 4.3 ac specifications ................................................................................................30 4.3.1 power and ground .................................................................................30 4.3.2 decoupling recommendations ..............................................................30 4.3.3 connection specifications ......................................................................31 4.3.4 ac timings.............................................................................................31 4.4 i/o buffer models ................................................................................................39 4.4.1 buffer model parameters .......................................................................41 4.4.2 signal quality specifications ..................................................................43 4.4.2.1 ringback ...................................................................................43 4.4.2.2 settling time .............................................................................44 figures 1 pentium ? processor with voltage reduction technology block diagram ............ 9 2 spga pentium ? processor with voltage reduction technology pinout (top side view)........................................................................................12 3 spga pentium ? processor with voltage reduction technology pinout (pin side view).........................................................................................13 4 296-pin staggered pin grid array package (spga) ..........................................25 5 technique for measuring case temperature (t c ) ..............................................26 6 clock waveform ..................................................................................................35 7 valid delay timings.............................................................................................35 8 float delay timings.............................................................................................36 9 setup and hold timings ......................................................................................36
embedded pentium ? processor with voltage reduction technology 4 datasheet 10 reset and configuration timings........................................................................ 37 11 test timings........................................................................................................ 38 12 test reset timings ............................................................................................. 38 13 input buffer model, except special group .......................................................... 39 14 input buffer model for special group.................................................................. 40 15 first-order output buffer model.......................................................................... 41 16 overshoot/undershoot and ringback guidelines ............................................... 43 17 settling time ....................................................................................................... 44 tables 1 signals removed from the pentium ? processor with voltage reduction technology ........................................................................... 11 2 pin cross-reference by pin name address and data pins ........................... 14 3 pin cross-reference by pin name control pins ............................................ 15 4 no connect, power and ground pins ................................................................. 16 5 pin quick reference ........................................................................................... 17 6 output pins ......................................................................................................... 22 7 input pins ............................................................................................................ 23 8 input/output pins ................................................................................................ 24 9 pin functional grouping...................................................................................... 24 10 296-pin staggered pin grid array package dimensions key............................. 25 11 power dissipation requirements for thermal solution design .......................... 26 12 thermal resistances for embedded pentium ? processors with voltage reduction technology.................................................................... 27 13 absolute maximum ratings ................................................................................ 28 14 dc specifications................................................................................................ 29 15 3.3-v (5-v safe) dc specifications..................................................................... 29 16 input and output characteristics......................................................................... 29 17 ac specifications ................................................................................................ 31 18 notes for table 17 ............................................................................................... 34 19 parameters used in the specification of the first order input buffer model ...... 40 20 parameters used in the specification of the first-order output buffer model ... 41 21 buffer selection chart ......................................................................................... 41 22 signal to buffer type........................................................................................... 42 23 input, output and bidirectional buffer model parameters................................... 42 24 input buffer model parameters: d (diodes) ........................................................ 42
datasheet 5 embedded pentium ? processor with voltage reduction technology revision history date revision description 11/12/98 001 this is the first publication of this document

embedded pentium ? processor with voltage reduction technology datasheet 7 1.0 introduction the intel ? embedded pentium ? processor with voltage reduction technology is a reduced power version of the embedded pentium processor. voltage reduction technology allows the processor to interface with industry standard 3.3-volt components while its inner core, operating at 3.1 volts, consumes less power. the embedded pentium processor with voltage reduction technology is available in a staggered pin grid array (spga) package. it has all the advanced features of the original pentium processor except for the differences listed in differences from the pentium processor on page 10. the embedded pentium processor with voltage reduction technology has several features that are ideal for embedded applications, including: ? 3.1-v core and 3.3-v i/o buffer v cc inputs reduce power consumption significantly, while maintaining 3.3-v compatibility externally. ? the sl enhanced feature set, which was initially implemented in the intel486 ? processor family. the architecture and internal features of the embedded pentium processor with voltage reduction technology are identical to the embedded pentium processor specifications provided in the embedded pentium ? processor family developers manual (order number 273204), except that several features have been eliminated to streamline it for embedded applications. this document should be used in conjunction with the following related embedded pentium processor documents. ? embedded pentium ? processor family developers manual (order number: 273204) ? intel architecture software developers manual , volumes 1C3 (order numbers 243190, 243191, and 243192) 2.0 architecture overview the embedded pentium processor with voltage reduction technology extends the intel pentium family of microprocessors. the embedded pentium processor family consists of the embedded pentium processor, the embedded pentium processor with voltage reduction technology described in this document, the embedded pentium processor with mmx? technology, and the low-power embedded pentium processor with mmx technology. pentium processor is used in this document to refer to the entire pentium processor family in general. the embedded pentium processor family architecture contains all the features of the intel486 processor family, and provides significant enhancements including the following: ? superscalar architecture ? dynamic branch prediction ? pipelined floating-point unit ? improved instruction execution time ? separate 8-kbyte code and 8-kbyte data caches ? writeback mesi protocol in the data cache ? 64-bit data bus ? bus cycle pipelining
embedded pentium ? processor with voltage reduction technology 8 datasheet ? address parity ? internal parity checking ? execution tracing ? performance monitoring ? ieee 1149.1 boundary scan ? system management mode ? virtual mode extensions ? voltage reduction technology ? sl power management features 2.1 pentium ? processor family architecture the application instruction set of the pentium processor family includes the complete intel486 processor family instruction set with extensions to accommodate some of the additional functionality of the pentium processor. all application software written for the intel386 and intel486 family microprocessors runs on pentium processors without modification. the on-chip memory management unit is completely compatible with the intel386 family and intel486 family of processors. pentium processors implement several enhancements to increase performance. the two instruction pipelines and the floating-point unit are capable of independent operation. each pipeline issues frequently used instructions in a single clock. together, the dual pipes can issue two integer instructions in one clock, or one floating-point instruction (under certain circumstances, two floating-point instructions) in one clock. branch prediction is implemented in pentium processors. to support this, the processor has two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the btb so the needed code is almost always prefetched before it is needed for execution. the floating-point unit (fpu) is up to ten times faster than the fpu used on the intel486 processor for common operations including add, multiply, and load. pentium processors include separate code and data caches integrated on-chip to meet performance goals. each cache is 8 kbytes with a 32-byte line size, and is two-way set associative. each cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to physical addresses. the data cache is configurable to be write back or write through on a line-by-line basis and follows the mesi protocol. the data cache tags are triple-ported to support two data transfers and an inquire cycle in the same clock. the code cache is an inherently write-protected cache. the code cache tags are also triple-ported to support snooping and split-line accesses. individual pages can be configured as cacheable or non-cacheable by software or hardware. the cache can be enabled or disabled by software or hardware. pentium processors have a 64-bit data bus for fast data transfer. burst read and burst writeback cycles are supported. in addition, bus cycle pipelining has been added to allow two bus cycles to occur simultaneously. the memory management unit contains optional extensions to the architecture which allow 2-mbyte and 4-mbyte page sizes. pentium processors have added significant data integrity and error detection capability. data parity checking is still supported on a byte-by-byte basis. address parity checking and internal parity checking features have been added along with a new exception, the machine check exception.
embedded pentium ? processor with voltage reduction technology datasheet 9 in addition, pentium processors have implemented functional redundancy checking to provide maximum error detection of the processor and the interface to the processor. when functional redundancy checking is used, a second processor, the checker executes in lock-step with the master processor. the checker samples the masters outputs, compares those values with the values it computes internally, and asserts an error signal if a mismatch occurs. as more and more functions are integrated on-chip, the complexity of board level testing is increased. to address this, pentium processors have increased test and debug capability. pentium processors implement ieee boundary scan (standard 1149.1). in addition, pentium processors provide four breakpoint pins that correspond to each of the debug registers and externally indicate a breakpoint match. execution tracing provides external indications when an instruction has completed execution in either of the two internal pipelines, or when a branch has been taken. system management mode (smm) has been implemented along with some extensions to the smm architecture. enhancements to the virtual 8086 mode have been made to increase performance by reducing the number of times it is necessary to trap to a virtual 8086 monitor. figure 1 is a block diagram of the embedded pentium processor with voltage reduction technology. figure 1. pentium ? processor with voltage reduction technology block diagram a6054-01 control rom control unit address generate (u pipeline) address generate (v pipeline) bus unit 64-bit data bus 32-bit address bus control tlb data cache 8 kbytes branch target buffer prefetch address instruction pointer prefetch buffers instruction decode code cache 8 kbytes tlb 256 64 32 32 32 32 32 32 80 80 control add floating point unit register file 64-bit data bus 32-bit addr. bus 32 integer register file alu (u pipline) alu (v pipline) barrel shifter branch verification and target address divide multiply page unit
embedded pentium ? processor with voltage reduction technology 10 datasheet the block diagram shows the two instruction pipelines, the u pipe and the v pipe. the u-pipe can execute all integer and floating-point instructions. the v-pipe can execute simple integer instructions and the fxch floating-point instructions. the separate code and data caches are shown. the data cache has two ports, one for each of the two pipes (the tags are triple-ported to allow simultaneous inquire cycles). the data cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to the physical addresses used by the data cache. the code cache, branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units. instructions are fetched from the code cache or from the external bus. branch addresses are remembered by the branch target buffer. the code cache tlb translates linear addresses to physical addresses used by the code cache. the decode unit decodes the prefetched instructions so the processor can execute the instruction. the control rom contains microcode to control the sequence of operations that must be performed to implement the pentium processor architecture. the control rom unit has direct control over both pipelines. pentium processors contain a pipelined floating-point unit that provides a significant floating-point performance advantage over previous generations of processors. the pentium processor supports clock control. when the clock to the processor is stopped, power dissipation is virtually eliminated. this makes the pentium processor a good choice for energy- efficient designs. the pentium processor supports fractional bus operation. this allows the processor core to operate at high frequencies, while communicating with the external bus at lower frequencies. the pentium processor contains an on-chip advanced programmable interrupt controller (apic). this apic implementation supports multiprocessor interrupt management (with symmetric interrupt distribution across all processors), multiple i/o subsystem support, 8259a compatibility, and inter-processor interrupt support. the processors architectural features are more fully described in the embedded pentium ? processor family developers manual (order number 273204). 3.0 packaging information 3.1 differences from the pentium processor to better streamline the processor for embedded applications, the following features have been eliminated from the embedded pentium processor with voltage reduction technology: upgrade, dual processing (dp), apic and master/checker functional redundancy. table 1 lists the corresponding pins that exist on the spga 3.3-v pentium processor but have been removed from the embedded pentium processor with voltage reduction technology.
embedded pentium ? processor with voltage reduction technology datasheet 11 3.2 pinout the embedded pentium processor with voltage reduction technology package has a pin array that is mechanically identical to the spga version of the 3.3-v pentium processor, but some pins need to be connected differently. table 1 lists the spga embedded pentium processor with voltage reduction technology pins that are different from the spga 3.3-v pentium processor. the signals listed in table 1 are now no connect pins on the embedded pentium processor with voltage reduction technology. leave these pins unconnected. table 4 includes the list of nc pins. connection of these pins may result in component failure or incompatibility with processor steppings. note: the v cc2 pins are 3.1 v for the spga embedded pentium processor with voltage reduction technology. figure 2 is the pin side spga pinout diagram. for a brief functional description of the pins, refer to table 5. additional input and output pin information is provided in table 6, table 7, and table 8. table 1. signals removed from the pentium ? processor with voltage reduction technology signal function adsc# additional address status. this signal is mainly used for large or standalone l2 cache memory subsystem support required for high-performance desktop or server models. brdyc# additional burst ready. this signal is mainly used for large or standalone l2 cache memory subsystem support required for high-performance desktop or server models. cputyp cpu type. this signal is used for dual processing systems. d/p# dual/primary processor identification. this signal is only used for an upgrade processor. frcmc# functional redundancy checking. this signal is only used for error detection via processor redundancy, and requires two pentium processors (master/checker). pbgnt# private bus grant. this signal is only used for dual processing systems. pbreq# private bus request. this signal is used only for dual processing systems. phit# private hit. this signal is only used for dual processing systems. phitm# private modified hit. this signal is only used for dual processing systems. picclk apic clock. this signal is the apic interrupt controller serial data bus clock. picd0 [dpen#] apics programmable interrupt controller data line 0. picd0 shares a pin with dpen# (dual processing enable). picd1 [apicen] apics programmable interrupt controller data line 1. picd1 shares a pin with apicen (apic enable (on reset)).
embedded pentium ? processor with voltage reduction technology 12 datasheet figure 2. spga pentium ? processor with voltage reduction technology pinout (top side view) a6055-01 37 35 33 36 34 32 30 28 31 29 272625242322212019181716151413121110987654321 37 35 be6# nc nc v cc3 v cc3 nc r v ss v cc3 t s v ss v cc3 v cc3 nc nc v cc3 v ss stpclk# v u w nc bf0 v cc3 v ss bf1 x v ss pen# z y ignne# init v cc3 na# nc v cc2 wb/wt# nc v cc2 brdy# v ss boff# v ss prdy nc v cc2 r/s# nmi v cc3 hold v ss v ss smi# ab aa ac ad ae apchk# nc v cc2 nc a23 v cc3 nc v ss v ss intr pcd smiact# v cc2 a24 a27 v cc3 pchk# v ss v ss a21 af ag ah aj ads# hlda breq a25 a31 v ss lock# v ss a22 a26 be2# hitm# be0# buschk# be4# pwt inc a11 nc scyc a3 a7 v ss a12 a14 a16 a18 a20 be7# be3# hit# be1# a20m# be5# d/c# ap a5 reset clk a28 a29 a9 a13 a15 a17 a19 v cc2 33 al ak al am an an view of component as mounted on board (pins down) v cc2 inc v cc2 flush# v cc2 inc inc 36 34 32 30 28 31 29 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10987654321 a10 v cc2 v cc2 nc a6 v ss v cc3 v cc3 v cc3 v cc3 v cc3 v ss am v ss w/r# v ss v ss v ss eads# nc a8 v ss v ss a30 a4 v ss v ss v ss v ss v ss d d4 d5 f e d1 d3 v cc3 d2 nc v cc3 v ss nc h g j nc v cc3 v cc3 v ss d0 k v ss tck m l tdi tdo v cc3 v ss tms p n q d6 d7 v cc3 trst# v ss nc dp0 d8 r t s v u w x z y ab aa ac ad ae af ag ah aj ak d f e h g j k m l p n q c b a dp7 d63 v cc2 ferr# pm0bp0 v cc2 d62 v ss ierr# v ss bp3 bp2 v cc2 pm1bp1 v ss inv cache# v cc2 mi/o# v ss ken# ewbe# v cc2 ahold v ss d49 d52 d54 d53 d55 v cc2 d48 d50 d51 dp6 d58 d57 v cc2 d56 v ss d60 d61 v cc2 d59 v ss dp5 d42 d46 d30 d33 d40 d44 dp3 dp1 d26 d28 d12 d19 d23 d37 d39 d35 c b a d10 d14 d47 inc d29 d32 dp4 d45 d31 d21 d25 d27 d17 d24 dp2 d36 d38 d34 d9 d11 d13 d43 inc v ss v ss v ss v ss v ss d20 v ss v ss d16 v ss v ss v ss v ss v ss d15 d18 d41 inc v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 v cc3 v cc3 v cc3 v cc3 v cc3 v cc3 d22 nc
embedded pentium ? processor with voltage reduction technology datasheet 13 figure 3. spga pentium ? processor with voltage reduction technology pinout (pin side view) a6056-01 37 35 33 36 34 32 30 28 31 29 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 37 35 be6# nc nc v cc3 v cc3 nc r v ss v cc3 t s v ss v cc3 v cc3 nc nc v cc3 v ss stpclk# v u w nc bf0 v cc3 v ss bf1 x v ss pen# z y ignne# init v cc3 na# nc v cc2 wb/wt# nc v cc2 brdy# v ss boff# v ss prdy nc v cc2 r/s# nmi v cc3 hold v ss v ss smi# ab aa ac ad ae apchk# nc v cc2 nc a23 v cc3 nc v ss v ss intr pcd smiact# v cc2 a24 a27 v cc3 pchk# v ss v ss a21 af ag ah aj ads# hlda breq a25 a31 v ss lock# v ss a22 a26 be2# hitm# be0# buschk# be4# pwt inc a11 nc scyc a3 a7 v ss a12 a14 a16 a18 a20 be7# be3# hit# be1# a20m# be5# d/c# ap a5 reset clk a28 a29 a9 a13 a15 a17 a19 v cc2 33 al ak al am an an pin side view v cc2 inc v cc2 flush# v cc2 inc inc 36 34 32 30 28 31 29 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a10 v cc2 v cc2 nc a6 v ss v cc3 v cc3 v cc3 v cc3 v cc3 v ss am v ss w/r# v ss v ss v ss eads# nc a8 v ss v ss a30 a4 v ss v ss v ss v ss v ss d d4 d5 f e d1 d3 v cc3 d2 nc v cc3 v ss nc h g j nc v cc3 v cc3 v ss d0 k v ss tck m l tdi tdo v cc3 v ss tms p n q d6 d7 v cc3 trst# v ss nc dp0 d8 r t s v u w x z y ab aa ac ad ae af ag ah aj ak d f e h g j k m l p n q c b a dp7 d63 v cc2 ferr# pm0bp0 v cc2 d62 v ss ierr# v ss bp3 bp2 v cc2 pm1bp1 v ss inv cache# v cc2 mi/o# v ss ken# ewbe# v cc2 ahold v ss d49 d52 d54 d53 d55 v cc2 d48 d50 d51 dp6 d58 d57 v cc2 d56 v ss d60 d61 v cc2 d59 v ss dp5 d42 d46 d30 d33 d40 d44 dp3 dp1 d26 d28 d12 d19 d23 d37 d39 d35 c b a d10 d14 d47 inc d29 d32 dp4 d45 d31 d21 d25 d27 d17 d24 dp2 d36 d38 d34 d9 d11 d13 d43 inc v ss v ss v ss v ss v ss d20 v ss v ss d16 v ss v ss v ss v ss v ss d15 d18 d41 inc v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 v cc3 v cc3 v cc3 v cc3 v cc3 v cc3 d22 nc
embedded pentium ? processor with voltage reduction technology 14 datasheet 3.2.1 pin cross reference table 2. pin cross-reference by pin name address and data pins pin location pin location pin location pin location pin location address a3 al35 a9 ak30 a15 ak26 a21 af34 a27 ag33 a4 am34 a10 an31 a16 al25 a22 ah36 a28 ak36 a5 ak32 a11 al31 a17 ak24 a23 ae33 a29 ak34 a6 an33 a12 al29 a18 al23 a24 ag35 a30 am36 a7 al33 a13 ak28 a19 ak22 a25 aj35 a31 aj33 a8 am32 a14 al27 a20 al21 a26 ah34 data d0 k34 d13 b34 d26 d24 d39 d10 d52 e03 d1 g35 d14 c33 d27 c21 d40 d08 d53 g05 d2 j35 d15 a35 d28 d22 d41 a05 d54 e01 d3 g33 d16 b32 d29 c19 d42 e09 d55 g03 d4 f36 d17 c31 d30 d20 d43 b04 d56 h04 d5 f34 d18 a33 d31 c17 d44 d06 d57 j03 d6 e35 d19 d28 d32 c15 d45 c05 d58 j05 d7 e33 d20 b30 d33 d16 d46 e07 d59 k04 d8 d34 d21 c29 d34 c13 d47 c03 d60 l05 d9 c37 d22 a31 d35 d14 d48 d04 d61 l03 d10 c35 d23 d26 d36 c11 d49 e05 d62 m04 d11 b36 d24 c27 d37 d12 d50 d02 d63 n03 d12 d32 d25 c23 d38 c09 d51 f04
embedded pentium ? processor with voltage reduction technology datasheet 15 table 3. pin cross-reference by pin name control pins pin location pin location pin location pin location a20m# ak08 nc y03 flush# an07 pen# z34 ads# aj05 breq aj01 hit# ak06 pm0/bp0 q03 nc am02 buschk# al07 hitm# al05 pm1/bp1 r04 ahold v04 cache# u03 hlda aj03 prdy ac05 ap ak02 nc q35 hold ab04 pwt al03 apchk# ae05 d/c# ak04 ierr# p04 r/s# ac35 be0# al09 nc ae35 ignne# aa35 reset ak20 be1# ak10 dp0 d36 init aa33 scyc al17 be2# al11 dp1 d30 intr/lint0 ad34 smi# ab34 be3# ak12 dp2 c25 inv u05 smiact# ag03 be4# al13 dp3 d18 ken# w05 tck m34 be5# ak14 dp4 c07 lock# ah04 tdi n35 be6# al15 dp5 f06 m/io# t04 tdo n33 be7# ak16 dp6 f02 na# y05 tms p34 boff# z04 dp7 n05 nmi/lint1 ac33 trst# q33 bp2 s03 eads# am04 pcd ag05 w/r# am06 bp3 s05 ewbe# w03 pchk# af04 wb/wt# aa05 brdy# x04 ferr# q05 clock control clk ak18 bf0 y33 bf1 y35 stpclk# v34
embedded pentium ? processor with voltage reduction technology 16 datasheet 3.2.2 design notes for reliable operation, always connect unused inputs to an appropriate signal level. unused active low inputs should be connected to v cc3 . unused active high inputs should be connected to gnd (v ss ). no connect (nc) pins must remain unconnected. connection of nc pins may result in component failure or incompatibility with processor steppings. 3.2.3 pin quick reference this section gives a brief functional description of each pin. for a detailed description, see the hardware interface chapter in the embedded pentium ? processor family developers manual (order number 273204). note that all input pins must meet their ac/dc specifications to guarantee proper functional behavior. the # symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage. when a # symbol is not present after the signal name, the signal is active, or asserted at the high voltage level. table 4. no connect, power and ground pins v cc2 1 a07 a17 q01 aa01 an19 a09 g01 s01 ac01 an15 a11 j01 u01 ae01 ag01 a13 l01 w01 an11 an09 a15 n01 y01 an13 an17 v cc3 a19 aa37 an25 l33 u33 a21 ac37 an27 l37 u37 a23 ae37 an29 n37 w37 a25 ag37 e37 q37 y37 a27 an21 g37 s37 a29 an23 j37 t34 no connect (nc) 2 a37 ae03 an35 q35 w33 aa03 ae35 h34 r34 w35 ac03 al19 j33 s33 y03 ad04 am02 l35 s35 note: 1. these v cc2 pins are 3.3-v v cc pins for the spga 3.3-v pentium ? processor. for the spga embedded pentium processor with voltage reduction technology, these pins are 3.1-v v cc2 supplies for the spga core. 2. these nc pins should be left unconnected. connection of these pins may result in component failure or incompatibility with processor steppings.
embedded pentium ? processor with voltage reduction technology datasheet 17 table 5. pin quick reference symbol type function a20m# i when the address bit 20 mask pin is asserted, the pentium ? processor emulates the address wraparound at 1 mbyte that occurs on the 8086. when a20m# is asserted, the processor masks physical address bit 20 (a20) before performing a lookup to the internal caches or driving a memory cycle on the bus. the effect of a20m# is undefined in protected mode. a20m# must be asserted only when the processor is in real mode. a31Ca3 i/o as outputs, the address lines of the processor along with the byte enables define the physical area of memory or i/o accessed. the external system drives the inquire address to the processor on a31Ca5. ads# o the address status indicates that a new valid bus cycle is currently being driven by the processor. ahold i in response to the assertion of address hold , the processor will stop driving the address lines (a31-a3), and ap in the next clock. the rest of the bus will remain active so data can be returned or driven for previously issued bus cycles. ap i/o address parity is driven by the processor with even parity information on all processor generated cycles in the same clock in which the address is driven. even parity must be driven back to the processor during inquire cycles on this pin in the same clock as eads# to ensure that the correct parity check status is indicated. apchk# o the address parity check status pin is asserted two clocks after eads# is sampled active if the processor has detected a parity error on the address bus during inquire cycles. apchk# will remain active for one clock each time a parity error is detected. be7#Cbe5# be4#Cbe0# o i/o the byte enable pins are used to determine which bytes must be written to external memory, or which bytes were requested by the processor for the current cycle. the byte enables are driven in the same clock as the address lines (a31Ca3). bf1Cbf0 i bus frequency determines the bus-to-core ratio. the bus frequency pins are sampled at reset, and cannot be changed until another non-warm (1 ms) assertion of reset. additionally, bf must not change values while reset is active. for proper operation of the embedded pentium processor with voltage reduction technology, the bf1 pin should be strapped high, and the bf0 pin should be strapped low. this sets the bus-to-core ratio at 1/2. other combinations are reserved. boff# i the backoff input is used to abort all outstanding bus cycles that have not yet completed. in response to boff#, the processor will float all pins normally floated during bus hold in the next clock. the processor remains in bus hold until boff# is negated, at which time the processor restarts the aborted bus cycle(s) in their entirety. bp3Cbp2 pm1/bp1C pm0/bp0 o the breakpoint pins (bp3Cbp0) correspond to the debug registers, dr3Cdr0. these pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches. bp1 and bp0 are multiplexed with the performance monitoring pins (pm1 and pm0). the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. brdy# i the burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the processor data in response to a write request. this signal is sampled in the t2, t12 and t2p bus states. breq o the bus request output indicates to the external system that the processor has internally generated a bus request. this signal is always driven whether or not the processor is driving its bus.
embedded pentium ? processor with voltage reduction technology 18 datasheet buschk# i the bus check input allows the system to signal an unsuccessful completion of a bus cycle. if this pin is sampled active, the processor will latch the address and control signals in the machine check registers. if, in addition, the mce bit in cr4 is set, the processor will vector to the machine check exception. cache# o for processor-initiated cycles, the cache pin indicates internal cacheability of the cycle (if a read), and indicates a burst writeback cycle (if a write). if this pin is driven inactive during a read cycle, the processor does not cache the returned data, regardless of the state of the ken# pin. this pin is also used to determine the cycle length (number of transfers in the cycle). clk i the clock input provides the fundamental timing for the processor. its frequency is the operating frequency of the processors external bus and requires ttl levels. all external timing parameters except tdi, tdo, tms, and trst# are specified with respect to the rising edge of clk. it is recommended that clk begin 150 ms after v cc reaches its proper operating level. this recommendation is only to assure the long term reliability of the device. d/c# o the data/code output is one of the primary bus cycle definition pins. it is driven valid in the same clock in which the ads# signal is asserted. d/c# distinguishes between data and code or special cycles. d63Cd0 i/o these are the 64 data lines for the processor. lines d7Cd0 define the least significant byte of the data bus; lines d63Cd56 define the most significant byte of the data bus. when the processor is driving the data lines, they are driven during the t2, t12 or t2p clocks for that cycle. during reads, the processor samples the data bus when brdy# is returned. dp7Cdp0 i/o these are the data parity pins for the processor. there is one for each byte of the data bus. they are driven by the processor with even parity information on writes in the same clock as write data. even parity information must be driven back to the embedded pentium processor with voltage reduction technology on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the processor. dp7 applies to d63Cd56; dp0 applies to d7Cd0. eads# i this signal indicates that a valid external address has been driven onto the processor address pins to be used for an inquire cycle. ewbe# i the external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the external system. when the processor generates a write and ewbe# is sampled inactive, the processor will hold off all subsequent writes to all e- or m-state lines in the data cache until all write cycles have completed, as indicated by ewbe# being active. ferr# o the floating-point error pin is driven active when an unmasked floating-point error occurs. ferr# is similar to the error# pin on the intel387? math coprocessor. ferr# is included for compatibility with systems using dos-type floating-point error reporting. flush# i when asserted, the cache flush input forces the processor to write back all modified lines in the data cache and invalidate its internal caches. a flush acknowledge special cycle is generated by the processor indicating completion of the writeback and invalidation. if flush# is sampled low when reset transitions from high to low, three-state test mode is entered. hit# o the hit indication is driven to reflect the outcome of an inquire cycle. if an inquire cycle hits a valid line in either the data or instruction cache, this pin is asserted two clocks after eads# is sampled asserted. if the inquire cycle misses the cache, this pin is negated two clocks after eads#. this pin changes its value only as a result of an inquire cycle and retains its value between the cycles. table 5. pin quick reference symbol type function
embedded pentium ? processor with voltage reduction technology datasheet 19 hitm# o the hit to a modified line output is driven to reflect the outcome of an inquire cycle. it is asserted after an inquire cycle that results in a hit to a modified line in the data cache. it is used to inhibit another bus master from accessing the data until the line is completely written back. hlda o the bus hold acknowledge pin goes active in response to a hold request driven to the processor on the hold pin. it indicates that the processor has floated most of the output pins and relinquished the bus to another local bus master. when leaving bus hold, hlda is driven inactive and the processor resumes driving the bus. if the processor has a bus cycle pending, it will be driven in the same clock in which hlda is deasserted. hold i in response to the bus hold request , the processor will float most of its output and input/output pins and assert hlda after completing all outstanding bus cycles. the processor will maintain its bus in this state until hold is deasserted. hold is not recognized during lock cycles. the processor will recognize hold during reset. ierr# o the internal error pin is used to indicate internal parity errors. if a parity error occurs on a read from an internal array, the processor will assert the ierr# pin for one clock and then shutdown. ignne# i the ignore numeric error input has no effect when the ne bit in cr0 is set to 1. when the cr0.ne bit is 0 and the ignne# pin is asserted, the processor ignores any pending unmasked numeric exception and continues executing floating-point instructions for the entire duration that this pin is asserted. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one of finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the processor will execute the instruction in spite of the pending exception. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one other than finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the processor will stop execution and wait for an external interrupt. init i the processor initialization input pin forces the processor to begin execution in a known state. the processor state after init is the same as the state after reset except that the internal caches, write buffers, and floating-point registers retain the values they had prior to init. init may not be used in lieu of reset after power up. if init is sampled high when reset transitions from high to low, the processor will perform built-in self test prior to the start of program execution. intr i an active maskable interrupt input indicates that an external interrupt has been generated. if the if bit in the eflags register is set, the processor will generate two locked interrupt acknowledge bus cycles and vector to an interrupt handler after the current instruction execution is completed. intr must remain active until the first interrupt acknowledge cycle is generated to ensure that the interrupt is recognized. inv i the invalidation input determines the final cache line state (s or i) in case of an inquire cycle hit. it is sampled together with the address for the inquire cycle in the clock in which eads# is sampled active. ken# i the cache enable pin is used to determine whether the current cycle is cacheable or not and is consequently used to determine cycle length. when the processor generates a cycle that can be cached (cache# asserted) and ken# is active, the cycle will be transformed into a burst line fill cycle. lock# o the bus lock pin indicates that the current bus cycle is locked. the processor does not allow a bus hold when lock# is asserted (but ahold and boff# are allowed). lock# goes active in the first clock of the first locked bus cycle and goes inactive after the brdy# is returned for the last locked bus cycle. lock# is guaranteed to be deasserted for at least one clock between back-to-back locked cycles. table 5. pin quick reference symbol type function
embedded pentium ? processor with voltage reduction technology 20 datasheet m/io# o the memory/input-output is one of the primary bus cycle definition pins. it is driven valid in the same clock in which the ads# signal is asserted. m/io# distinguishes between memory and i/o cycles. na# i an active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. the processor will issue ads# for a pending cycle two clocks after na# is asserted. the processor supports up to two outstanding bus cycles. nmi i the non-maskable interrupt request signal indicates that an external non- maskable interrupt has been generated. pcd o the page cache disable pin reflects the state of the pcd bit in cr3, page directory entry or page table entry. the purpose of pcd is to provide an external cacheability indication on a page-by-page basis. pchk# o the parity check output indicates the result of a parity check on a data read. it is driven with parity status two clocks after brdy# is returned. pchk# remains low one clock for each clock in which a parity error was detected. parity is checked only for the bytes on which valid data is returned. pen# i the parity enable input (along with cr4.mce) determines whether a machine check exception will be taken as a result of a data parity error on a read cycle. if this pin is sampled active in the clock, a data parity error is detected. the processor will latch the address and control signals of the cycle with the parity error in the machine check registers. if, in addition, the machine check enable bit in cr4 is set to 1, the processor will vector to the machine check exception before the beginning of the next instruction. pm1/bp1C pm0/bp0 o these pins function as part of the performance monitoring feature. the breakpoint 1 C 0 pins are multiplexed with the performance monitoring 1-0 pins. the pb1 and pb0 bits in the debug mode control register determine whether the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. prdy o the probe ready output pin indicates that the processor has stopped normal execution in response to the r/s# pin going active or probe mode being entered. pwt o the page writethrough pin reflects the state of the pwt bit in cr3, the page directory entry, or the page table entry. the pwt pin is used to provide an external writeback indication on a page-by-page basis. r/s# i the run/stop input is an asynchronous, edge-sensitive interrupt used to stop the normal execution of the processor and place it into an idle state. a high to low transition on the r/s# pin will interrupt the processor and cause it to stop execution at the next instruction boundary. reset i reset forces the processor to begin execution at a known state. all the processor internal caches will be invalidated upon the reset. modified lines in the data cache are not written back. flush# and init are sampled when reset transitions from high to low to determine if three-state test mode will be entered or if bist will be run. scyc o the split cycle output is asserted during misaligned locked transfers to indicate that more than two cycles will be locked together. this signal is defined for locked cycles only. it is undefined for cycles that are not locked. smi# i the system management interrupt causes a system management interrupt request to be latched internally. when the latched smi# is recognized on an instruction boundary, the processor enters system management mode. smiact# o an active system management interrupt active output indicates that the processor is operating in system management mode. table 5. pin quick reference symbol type function
embedded pentium ? processor with voltage reduction technology datasheet 21 stpclk# i assertion of the stop clock input signifies a request to stop the internal clock of the embedded pentium processor with voltage reduction technology thereby causing the core to consume less power. when the processor recognizes stpclk#, the processor will stop execution on the next instruction boundary, unless superseded by a higher priority interrupt, and generate a stop grant acknowledge cycle. when stpclk# is asserted, the processor will still respond to external snoop requests. tck i the testability clock input provides the clocking function for the processor boundary scan in accordance with the ieee boundary scan interface (standard 1149.1). it is used to clock state information and data into and out of the processor during boundary scan. tdi i the test data input is a serial input for the test logic. tap instructions and data are shifted into the processor on the tdi pin on the rising edge of tck when the tap controller is in an appropriate state. tdo o the test data output is a serial output of the test logic. tap instructions and data are shifted out of the processor on the tdo pin on tcks falling edge when the tap controller is in an appropriate state. tms i the value of the test mode select input signal sampled at the rising edge of tck controls the sequence of tap controller state changes. trst# i when asserted, the test reset input allows the tap controller to be asynchronously initialized. vcc2 i these pins are the 3.1 v power inputs to the embedded pentium processor with voltage reduction technology. vcc3 i these pins are the 3.3 v power inputs to the embedded pentium processor with voltage reduction technology. vss i these pins are the ground inputs to the embedded pentium processor with voltage reduction technology. w/r# o write/read is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. w/r# distinguishes between write and read cycles. wb/wt# i the writeback/writethrough input allows a data cache line to be defined as writeback or writethrough on a line-by-line basis. as a result, it determines whether a cache line is initially in the s or e state in the data cache. table 5. pin quick reference symbol type function
embedded pentium ? processor with voltage reduction technology 22 datasheet 3.2.4 pin reference tables table 6. output pins name active level when floated ads# low bus hold, boff# apchk# low be7#Cbe5# low bus hold, boff# breq high cache# low bus hold, boff# ferr# low hit# low hitm# low hlda high ierr# low lock# low bus hold, boff# m/io#, d/c#, w/r# n/a bus hold, boff# pchk# low bp3Cbp2, pm1/bp1, pm0/bp0 high prdy high pwt, pcd high bus hold, boff# scyc high bus hold, boff# smiact# low tdo n/a all states except shift-dr and shift-ir note: all output and input/output pins are floated during three-state test mode (except tdo).
embedded pentium ? processor with voltage reduction technology datasheet 23 table 7. input pins name active level synchronous/ asynchronous internal resistor qualified a20m# low asynchronous ahold high synchronous bf high synchronous/reset pullup boff# low synchronous brdy# low synchronous pullup bus state t2, t12, t2p buschk# low synchronous pullup brdy# clk n/a eads# low synchronous ewbe# low synchronous brdy# flush# low asynchronous hold high synchronous ignne# low asynchronous init high asynchronous intr high asynchronous inv high synchronous eads# ken# low synchronous first brdy#/na# na# low synchronous bus state t2,td,t2p nmi high asynchronous pen# low synchronous brdy# r/s# n/a asynchronous pullup reset high asynchronous smi# low asynchronous pullup stpclk# low asynchronous pullup tck n/a pullup tdi n/a synchronous/tck pullup tck tms n/a synchronous/tck pullup tck trst# low asynchronous pullup wb/wt# n/a synchronous first brdy#/na#
embedded pentium ? processor with voltage reduction technology 24 datasheet 3.2.5 pin grouping according to function table 9 organizes the pins with respect to their function. table 8. input/output pins name active level when floated 1 qualified (when an input) internal resistor a31Ca3 n/a address hold, bus hold, boff# eads# ap n/a address hold, bus hold, boff# eads# be4#Cbe0# low bus hold, boff# reset pulldown 2 d63Cd0 n/a bus hold, boff# brdy# dp7Cdp0 n/a bus hold, boff# brdy# notes: 1. all output and input/output pins are floated during three-state test mode (except tdo). 2. be3#Cbe0# have pulldowns during reset only. table 9. pin functional grouping function pins clock clk initialization reset, init, bf address bus a31Ca3, be7#Cbe0# address mask a20m# data bus d63Cd0 address parity ap, apchk# data parity dp7Cdp0, pchk#, pen# internal parity error ierr# system error buschk# bus cycle definition m/io#, d/c#, w/r#, cache#, scyc, lock# bus control ads#, brdy#, na# page cacheability pcd, pwt cache control ken#, wb/wt# cache snooping/consistency ahold, eads#, hit#, hitm#, inv cache flush flush# write ordering ewbe# bus arbitration boff#, breq, hold, hlda interrupts intr, nmi floating-point error reporting ferr#, ignne# system management mode smi#, smiact# tap port tck, tms, tdi, tdo, trst# breakpoint/performance monitoring pm0/bp0, pm1/bp1, bp3Cbp2 clock control stpclk# probe mode r/s#, prdy
embedded pentium ? processor with voltage reduction technology datasheet 25 3.3 mechanical specifications the embedded pentium processor with voltage reduction technology is offered in an spga package without a heat spreader. the package is mechanically equivalent to the package used on the 3.3-v pentium processor c2 stepping except that the spga embedded pentium processor with voltage reduction technology will use a metal lid instead of a ceramic lid, and has the dimensions shown in figure 4. figure 4. 296-pin staggered pin grid array package (spga) table 10. 296-pin staggered pin grid array package dimensions key millimeters inches symbol min max notes min max notes a 3.27 3.83 metal lid 0.129 0.151 metal lid a1 0.66 0.86 metal lid 0.026 0.034 metal lid a2 2.62 2.97 0.103 0.117 b 0.43 0.51 0.017 0.020 d 49.28 49.78 1.940 1.960 d1 45.59 45.85 1.795 1.805 d3 24.00 24.25 includes fillet 0.945 0.955 includes fillet e1 2.29 2.79 0.090 0.110 l 3.05 3.30 0.120 1.130 n 296 total pins 296 total pins s1 1.52 2.54 0.060 0.100 d d1 d3 d3 d1 d seating plane l 1.65 ref 2.29 1.52 ref. 45 index chamfer (index corner) a a1 a2 e1 s1 s1 ? b pin c3 bottom view (pin side up) side view
embedded pentium ? processor with voltage reduction technology 26 datasheet 3.4 thermal specifications the spga embedded pentium processor with voltage reduction technology is specified for proper operation when the case temperature, t case (t c ), is within the specified range of 0 c to 85 c. the power dissipation specification in table 11 is provided for designing thermal solutions for operation at a sustained maximum level. this is the worst-case power the device would dissipate in a system for a sustained period of time. this number is provided to assist in the design of a thermal solution for the device. 3.4.1 measuring thermal values to verify that the proper case temperature (t c ) is maintained for the embedded pentium processor with voltage reduction technology, it should be measured at the center of the package top surface (encapsulant). to minimize any measurement errors, the following techniques are recommended: ? use 36 gauge or finer diameter k, t, or j type thermocouples. intel's laboratory testing was done using a thermocouple made by omega (part number: 5tc-ttk-36-36). ? attach the thermocouple bead or junction to the center of the package top surface using highly thermally conductive cements. intel's laboratory testing was done by using omega bond (part number: ob-100). ? attach the thermocouple at a 90 angle as shown in figure 5. table 11. power dissipation requirements for thermal solution design parameter typical 1 max 2 unit notes active power dissipation 3.0C4.0 7.9 watts stop grant and auto halt powerdown power dissipation 1.3 watts note 3 stop clock power dissipation 0.02 0.05 watts note 4 notes: 1. this is the typical power dissipation in a system. this value was the average value measured in a system using a typical device at v cc2 = 3.1 v and v cc3 = 3.3 v running typical applications. this value is highly dependent upon the specific system configuration. 2. systems must be designed to thermally dissipate the maximum active power dissipation. it is determined using a worst-case instruction mix with v cc2 = 3.1 v and v cc3 = 3.3 v. the use of nominal v cc in this measurement takes into account the thermal time constant of the package. 3. stop grant/auto halt powerdown power dissipation is determined by asserting the stpclk# pin or executing the halt instruction. 4. stop clock power dissipation is determined by asserting the stpclk# pin and then removing the external clk input. figure 5. technique for measuring case temperature (t c )
embedded pentium ? processor with voltage reduction technology datasheet 27 3.4.2 thermal equations for the embedded pentium processor with voltage reduction technology, an ambient temperature, t a (air temperature around the processor), is not specified directly. the only requirement is that the case temperature (t c ) is met. to calculate t a values, use the following equations: t a = t c C (p * q ca ) q ca = q ja C q jc where, t a and t c = ambient and case temperature ( c) q ca = case-to-ambient thermal resistance ( c/w) q ja = junction-to-ambient thermal resistance ( c/w) q jc = junction-to-case thermal resistance ( c/w) p = maximum power consumption in watts (see table 11) table 12 lists the q ca values for the pentium processor with passive heatsinks. thermal data collection parameters: ? heatsinks are omnidirectional pin aluminum alloy ? features were based on standard extrusion practices for a given height ? pin size ranged from 50 to 129 mils ? pin spacing ranged from 93 to 175 mils ? base thickness ranged from 79 to 200 mils ? heatsink attach was 0.005" of thermal grease ? using an attach thickness of 0.002 improves performance by approximately 0.3 c/w table 12. thermal resistances for embedded pentium ? processors with voltage reduction technology heatsink height in inches q jc (c/watt) q ca (c/watt) vs. laminar airflow (linear ft/min) 0 100 200 400 600 800 0.25 1.25 9.4 8.3 6.9 4.7 3.9 3.3 0.35 1.25 9.1 7.8 6.3 4.3 3.6 3.1 0.45 1.25 8.7 7.3 5.6 3.9 3.2 2.8 0.55 1.25 8.4 6.8 5.0 3.5 2.9 2.6 0.65 1.25 8.0 6.3 4.6 3.3 2.7 2.4 0.80 1.25 7.3 5.6 4.2 2.9 2.5 2.3 1.00 1.25 6.6 4.9 3.9 2.9 2.4 2.1 1.20 1.25 6.2 4.6 3.6 2.7 2.3 2.1 1.40 1.25 5.7 4.2 3.3 2.5 2.2 2.0 without heatsink 1.7 14.5 13.8 12.6 10.5 8.6 7.5
embedded pentium ? processor with voltage reduction technology 28 datasheet 4.0 electrical specifications 4.1 absolute maximum ratings the following values are stress ratings only. functional operation at the maximum ratings is not implied nor guaranteed. functional operating conditions are given in the ac and dc specification tables. extended operation beyond the maximum ratings may affect device reliability. furthermore, although the embedded pentium processor with voltage reduction technology contains protective circuitry to resist damage from static electric discharge, always take precautions to avoid high static voltages or electric fields. warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. 4.2 dc specifications tables 14, 15 and 16 list the dc specifications that apply to the embedded pentium processor with voltage reduction technology. the embedded pentium processor with voltage reduction technology core operates at 3.1 v internally while the i/o interface operates at 3.3 v. the clk input may be at 3.3 v or 5 v. since the 3.3-v (5-v safe) input levels defined in table 15 are the same as the 5-v ttl levels, the clk input is compatible with existing 5v clock drivers. table 13. absolute maximum ratings parameter maximum rating case temperature under bias - 65 c to 110 c storage temperature - 65 c to 150 c 3 v supply voltage with respect to v ss - 0.5 v to +4.6 v 3.1 v supply voltage with respect to v ss - 0.5 v to +4.1 v 3 v only buffer dc input voltage - 0.5 v to v cc3 +0.5; not to exceed 4.6 v 1 5 v safe buffer dc input voltage - 0.5 v to 6.5 v 2, 3 notes: 1. applies to all spga embedded pentium ? processor with voltage reduction technology inputs except clk. 2. applies to clk. 3. see table 15.
embedded pentium ? processor with voltage reduction technology datasheet 29 table 14. dc specifications t case = 0 to 85 c; v cc2 = 3.1 v 165 mv; v cc3 = 3.3 v 165 mv symbol parameter min max unit notes v il3 input low voltage - 0.3 0.8 v ttl level, note 1 v ih3 input high voltage 2.0 v cc3 +0.3 v ttl level, note 1 v ol3 output low voltage 0.4 v ttl level, note 1, note 2 v oh3 output high voltage 2.4 v ttl level, note 1, note 3 i cc2 power supply current from 3.1-v core supply 2775 ma note 4 i cc3 power supply current from 3.3-v i/o buffer supply 355 ma note 4 notes: 1. 3.3-v ttl levels apply to all signals except clk. 2. parameter measured at 4 ma. 3. parameter measured at 3 ma. 4. this value should be used for power supply design. it was estimated for a worst-case instruction mix and v cc2 = 3.1 v 165 mv and v cc3 = 3.3 v 165 mv. power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from stop clock to full active modes. table 15. 3.3-v (5-v safe) dc specifications symbol parameter min max unit notes v il5 input low voltage - 0.3 0.8 v ttl level; applies to clk only v ih5 input high voltage 2.0 5.55 v ttl level; applies to clk only table 16. input and output characteristics symbol parameter min max unit notes c in input capacitance 15 pf guaranteed by design. c o output capacitance 20 pf guaranteed by design. c i/o i/o capacitance 25 pf guaranteed by design. c clk clk input capacitance 15 pf guaranteed by design. c tin test input capacitance 15 pf guaranteed by design. c tout test output capacitance 20 pf guaranteed by design. c tck test clock capacitance 15 pf guaranteed by design. i li input leakage current 15 m a 0 < v in < v cc3 (for input without pull up or pull down resistors) i lo output leakage current 15 m a 0 < v in < v cc3 (for input without pull up or pull down resistors) i ih input leakage current 200 m a v in = 2.4 v (for input with pull down resistors) i il input leakage current - 400 m a v in = 0.4 v (for input with pull up resistors)
embedded pentium ? processor with voltage reduction technology 30 datasheet 4.2.1 power sequencing there is no specific sequence required for powering up or powering down the v cc2 and v cc3 power supplies. however, it is recommended that the v cc2 and v cc3 power supplies be either both on or both off within one second of each other. 4.3 ac specifications the ac specifications of the embedded pentium processor with voltage reduction technology consist of setup times, hold times, and valid delays at 0 pf. all embedded pentium processors with voltage reduction technology ac specifications are valid for v cc2 = 3.1 v + 165 mv, v cc3 = 3.3 v + 165 mv, and t case = 0o c to 85o c. 4.3.1 power and ground for clean on-chip power distribution, the embedded pentium processor with voltage reduction technology has 25 v cc2 (3.1-v power), 28 v cc3 (3.3-v power) and 53 v ss (ground) inputs. power and ground connections must be made to all external v cc2 , v cc3 and v ss pins of the processor. on the circuit board, all v cc2 pins must be connected to a 3.1-v v cc2 plane (or island) and all v cc3 pins must be connected to a 3.3-v v cc3 plane. all v ss pins must be connected to a v ss plane. refer to table 4 for a list of v cc2 and v cc3 pins. 4.3.2 decoupling recommendations transient power surges occur as the processor is executing instruction sequences or driving large loads. to mitigate these high frequency transients, liberal high frequency decoupling capacitors should be placed near the processor. low inductance capacitors and interconnects are recommended for best high frequency electrical performance. inductance can be reduced by minimizing the length of circuit board traces between the processor and the decoupling capacitors. these capacitors should be evenly distributed around each component on the 3.3-v plane and the 3.1-v plane (or island). capacitor values should be chosen to ensure that they eliminate both low and high frequency noise components. power transients also occur as the processor rapidly transitions from a low power consumption level to a much higher level (or high to low). a typical example would be entering or exiting the stop grant state. other examples include executing a halt instruction (which causes the processor to enter the auto halt powerdown state) or transitioning from halt to the normal state. all of these examples may cause abrupt changes in the power being consumed by the processor. note that the auto halt powerdown feature is always enabled even when other power management features are not implemented. several bulk storage capacitors with a low esr (effective series resistance) in the 10 to 100 f range are required to maintain a regulated supply voltage during the interval between the time the current load changes and the point at which the regulated power supply output can react to the change in load. in order to reduce the net esr, it may be necessary to place several bulk storage capacitors in parallel.
embedded pentium ? processor with voltage reduction technology datasheet 31 these capacitors should be placed near the processor (on the 3.3-v plane and the 3.1-v plane or island) to ensure that these supply voltages stay within specified limits during changes in the power demands of the processor during operation. for more detailed information, please contact intel or refer to the pentium ? processor with voltage reduction technology: power supply design considerations for mobile systems application note (order number 242558). note: capacitors degrade over time during use. as capacitors age, their capacity to store and hold a charge becomes compromised. designing a board with below minimum acceptable bypass and bulk capacitors may have future system reliability consequences. 4.3.3 connection specifications all nc pins must remain unconnected. refer to table 4 for a list of nc pins. for reliable operation, always connect unused inputs to an appropriate signal level. unused active low inputs should be connected to v cc3 . unused active high inputs should be connected to ground. 4.3.4 ac timings the ac specifications given in table 17 consist of output delays, input setup requirements and input hold requirements for the 66-mhz external bus. all ac specifications (with the exception of those for the tap signals and apic signals) are relative to the rising edge of the clk input. all timings are referenced to 1.5 v for both 0 and 1 logic levels unless otherwise specified. within the sampling window, a synchronous input must be stable for correct operation. table 17. ac specifications (sheet 1 of 4) v cc2 = 3.1 v 165 mv; v cc3 = 3.3 v 165 mv; t case = 0 c to 85 c; cl = 0 pf symbol parameter min max unit figure notes frequency 33.33 66.6 mhz t 1a clk period 15.0 30.0 ns 6 t 1b clk period stability 250 ps 1, 19 t 2 clk high time 4.0 ns 6 @2 v, note 1 t 3 clk low time 4.0 ns 6 @0.8 v, note 1 t 4 clk fall time 0.15 1.5 ns 6 2.0 vC0.8 v, note 1 t 5 clk rise time 0.15 1.5 ns 6 0.8 vC2.0 v, note 1 t 6a pwt, pcd, be7#Cbe0#, d/c#, w/r#, cache#, scyc valid delay 1.0 7.0 ns 7 t 6b ap valid delay 1.0 8.5 ns 7 t 6c lock# valid delay 1.1 7.0 ns 7 t 6d ads# valid delay 1.0 6.0 ns 7 t 6e a31Ca3 valid delay 1.1 6.3 ns 7 t 6f m/io# valid delay 1.0 5.9 ns 7 note: see table 18 for table notes.
embedded pentium ? processor with voltage reduction technology 32 datasheet t 7 ads#, ap, a31Ca3, pwt, pcd, be7#Cbe0#, m/io#, d/c#, w/r#, cache#, scyc, lock# float delay 10.0 ns 8 1 t 8a apchk#, ierr#, ferr# valid delay 1.0 8.3 ns 7 4 t 8b pchk# valid delay 1.0 7.0 ns 7 4 t 9a breq valid delay 1.0 8.0 ns 7 4 t 9b smiact# valid delay 1.0 7.3 ns 7 4 t 9c hlda valid delay 1.0 6.8 ns 7 4 t 10a hit# valid delay 1.0 6.8 ns 7 t 10b hitm# valid delay 1.1 6.0 ns 7 t 11a pm1Cpm0, bp3Cbp0 valid delay 1.0 10.0 ns 7 t 11b prdy valid delay 1.0 8.0 ns 7 t 12 d63Cd0, dp7Cdp0 write data valid delay 1.3 7.5 ns 7 t 13 d63Cd0, dp3Cdp0 write data float delay 10.0 ns 8 1 t 14 a31Ca5 setup time 6.0 ns 9 20 t 15 a31Ca5 hold time 1.0 ns 9 t 16a inv, ap setup time 5.0 ns 9 t 16b eads# setup time 5.0 ns 9 t 17 eads#, inv, ap hold time 1.0 ns 9 t 18a ken# setup time 5.0 ns 9 t 18b na#, wb/wt# setup time 4.5 ns 9 t 19 ken#, wb/wt#, na# hold time 1.0 ns 9 t 20 brdy# setup time 5.0 ns 9 t 21 brdy# hold time 1.0 ns 9 t 22 ahold, boff# setup time 5.5 ns 9 t 23 ahold, boff# hold time 1.0 ns 9 t 24a buschk#, ewbe#, hold, setup time 5.0 ns 9 t 24b pen# setup time 4.8 ns 9 t 25a buschk#, ewbe#, pen# hold time 1.0 ns 9 t 25b hold hold time 1.5 ns 9 t 26 a20m#, intr, stpclk# setup time 5.0 ns 9 11, 15 t 27 a20m#, intr, stpclk# hold time 1.0 ns 9 12 t 28 init, flush#, nmi, smi#, ignne# setup time 5.0 ns 9 11, 15, 16 table 17. ac specifications (sheet 2 of 4) v cc2 = 3.1 v 165 mv; v cc3 = 3.3 v 165 mv; t case = 0 c to 85 c; cl = 0 pf symbol parameter min max unit figure notes note: see table 18 for table notes.
embedded pentium ? processor with voltage reduction technology datasheet 33 t 29 init, flush#, nmi, smi#, ignne# hold time 1.0 ns 9 12 t 30 init, flush#, nmi, smi#, ignne# pulse width, async 2.0 clks 14, 16 t 31 r/s# setup time 5.0 ns 9 11, 15, 16 t 32 r/s# hold time 1.0 ns 9 12 t 33 r/s# pulse width, async. 2.0 clks 14, 16 t 34 d63Cd0, dp7Cdp0 read data setup time 2.8 ns 9 t 35 d63Cd0, dp7Cdp0 read data hold time 1.5 ns 9 t 36 reset setup time 5.0 ns 10 11, 15 t 37 reset hold time 1.0 ns 10 12 t 38 reset pulse width, v cc & clk stable 15.0 clks 10 16 t 39 reset active after v cc & clk stable 1.0 ms 10 power up t 40 reset configuration signals (init, flush#) setup time 5.0 ns 10 11, 15, 16 t 41 reset configuration signals (init, flush#) hold time 1.0 ns 10 12 t 42a reset configuration signals (init, flush#) setup time, async. 2.0 clks 10 to reset falling edge, note 15 t 42b reset configuration signals (init, flush#, brdy#, buschk#) hold time, async. 2.0 clks 10 to reset falling edge, note 21 t 42c reset configuration signal (brdy#, buschk#) setup time, async. 3.0 clks 10 to reset falling edge, note 21 t 43a bf setup time 1.0 ms 10 to reset falling edge, note 18 t 43b bf hold time 2.0 clks 10 to reset falling edge, note 18 t 43c be4# setup time 2.0 clks 10 to reset falling edge t 43d be4# hold time 2.0 clks 10 to reset falling edge t 44 tck frequency 16.0 mhz t 45 tck period 62.5 ns 6 t 46 tck high time 25.0 ns 6 @2 v, note 1 t 47 tck low time 25.0 ns 6 @0.8 v, note 1 t 48 tck fall time 5.0 ns 6 2.0 vC0.8 v, notes 1, 8, 9 t 49 tck rise time 5.0 ns 6 0.8 vC2.0 v, notes 1, 8, 9 table 17. ac specifications (sheet 3 of 4) v cc2 = 3.1 v 165 mv; v cc3 = 3.3 v 165 mv; t case = 0 c to 85 c; cl = 0 pf symbol parameter min max unit figure notes note: see table 18 for table notes.
embedded pentium ? processor with voltage reduction technology 34 datasheet t 50 trst# pulse width 40.0 ns 12 asynchronous, note 1 t 51 tdi, tms setup time 5.0 ns 11 7 t 52 tdi, tms hold time 13.0 ns 11 7 t 53 tdo valid delay 2.8 20.0 ns 11 8 t 54 tdo float delay 25.0 ns 11 1, 8 t 55 all non-test outputs valid delay 2.5 20.0 ns 11 3, 8, 10 t 56 all non-test outputs float delay 25.0 ns 11 1, 3, 8, 10 t 57 all non-test inputs setup time 5.0 ns 11 3, 7, 10 t 58 all non-test inputs hold time 13.0 ns 11 3, 7, 10 table 18. notes for table 17 notes: notes 2, 6 and 14 are general and apply to all standard ttl signals used with the pentium ? processor family. 1. not 100 percent tested. guaranteed by design. 2. ttl input test waveforms are assumed to be 0 to 3-v transitions with 1 v/ns rise and fall times. 3. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to boundary scan operations. 4. apchk#, ferr#, hlda, ierr#, lock#, and pchk# are glitch-free outputs. glitch-free signals monotonically transition without false transitions. 5. 0.8 v/ns clk input rise/fall time 8 v/ns. 6. 0.3 v/ns input rise/fall time 5 v/ns. 7. referenced to tck rising edge. 8. referenced to tck falling edge. 9. 1 ns can be added to the maximum tck rise and fall times for every 10 mhz of frequency below 33 mhz. 10. during probe mode operation, do not use the boundary scan timings (t 55C58 ). 11. setup time is required to guarantee recognition on a specific clock. 12. hold time is required to guarantee recognition on a specific clock. 13. all ttl timings are referenced from 1.5 v. 14. to guarantee proper asynchronous recognition, the signal must have been deasserted (inactive) for a minimum of two clocks before being returned active and must meet the minimum pulse width. 15. this input may be driven asynchronously. 16. when driven asynchronously, reset, nmi, flush#, r/s#, init, and smi# must be deasserted (inactive) for a minimum of two clocks before being returned active. 17. the d/c#, m/io#, w/r#, cache#, and a31Ca5 signals are sampled only on the clk in which ads# is active. 18. bf should be strapped to v cc3 or left floating. 19. these signals are measured on the rising edge of adjacent clks at 1.5 v. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 khz and 1/3 of the clk operating frequency. the amount of jitter present must be accounted for as a component of clk skew between devices. 20. timing (t 14 ) is required for external snooping (e.g., address setup to the clk in which eads# is sampled active). 21. buschk# is used as a reset configuration signal to select buffer size. 22. each valid delay is specified for a 0 pf load. the system designer should use i/o buffer modeling to account for signal flight time delays. table 17. ac specifications (sheet 4 of 4) v cc2 = 3.1 v 165 mv; v cc3 = 3.3 v 165 mv; t case = 0 c to 85 c; cl = 0 pf symbol parameter min max unit figure notes note: see table 18 for table notes.
embedded pentium ? processor with voltage reduction technology datasheet 35 figure 6. clock waveform figure 7. valid delay timings
embedded pentium ? processor with voltage reduction technology 36 datasheet figure 8. float delay timings figure 9. setup and hold timings
embedded pentium ? processor with voltage reduction technology datasheet 37 figure 10. reset and configuration timings
embedded pentium ? processor with voltage reduction technology 38 datasheet figure 11. test timings figure 12. test reset timings 1.5 v t r =t57 tck tdi tms tdo output signals input signals t v t w t x t y t r t s t u t z t s =t58 t u =t54 t v =t51 t w =t52 t x =t53 t y =t55 t z =t56
embedded pentium ? processor with voltage reduction technology datasheet 39 4.4 i/o buffer models this section describes the i/o buffer models of the embedded pentium processor with voltage reduction technology. the first-order i/o buffer model is a simplified representation of the complex input and output buffers used in the embedded pentium processor with voltage reduction technology. figure 13 and figure 14 show the structure of the input buffer model and figure 15 shows the output buffer model. table 19 and table 20 show the parameters used to specify these models. although simplified, these buffer models accurately model flight time and signal quality. for these parameters, there is very little added accuracy in the complete transistor model. the following two models represent the input buffer models. the first model, figure 13, represents all of the input buffers except for a special group of input buffers. the second model, figure 14, represents these special buffers: ahold, eads#, ken#, wb/wt#, inv, na#, ewbe#, boff# and clk. in addition to the input and output buffer parameters, input protection diode models are provided for added accuracy. these diodes have been optimized to provide esd protection and provide some level of clamping. although the diodes are not required for simulation, it may be more difficult to meet specifications without them. some signal quality specifications require that the diodes be removed from the input model. the series resistors (rs) are a part of the diode model. remove these when removing the diodes from the input model. figure 13. input buffer model, except special group note: vcc refers to the i/o buffer vcc3.
embedded pentium ? processor with voltage reduction technology 40 datasheet figure 15 shows the structure of the output buffer model. this model is used for all of the output buffers of the embedded pentium processor with voltage reduction technology. figure 14. input buffer model for special group table 19. parameters used in the specification of the first order input buffer model parameter description c in minimum and maximum value of the capacitance of the input buffer model l p minimum and maximum value of the package inductance c p minimum and maximum value of the package capacitance r s diode series resistance d1, d2 ideal diodes 6 x r d2 d2 d2 d2 d2 d2 d1 c p l p c in s r s v cc2 v ss
embedded pentium ? processor with voltage reduction technology datasheet 41 4.4.1 buffer model parameters this section gives the parameters for each embedded pentium processor with voltage reduction technology input, output and bidirectional signal, as well as the settings for the configurable buffers. some pins on the embedded pentium processor with voltage reduction technology have selectable buffer sizes. these pins use the configurable output buffer eb2. table 21 shows the drive level for brdy# required at the falling edge of reset to select the buffer strength. the buffer sizes selected should be the appropriate size required; otherwise ac timings might not be met, or too much overshoot and ringback may occur. there are no other selection choices; all of the configurable buffers get set to the same size during setup initialization. the input, output and bidirectional buffer values of the embedded pentium processor with voltage reduction technology are listed in table 23. this table contains listings for all three types; do not confuse them during simulation. when a bidirectional pin is operating as an input, use the c in , c p and l p values; when it is operating as a driver, use all of the data parameters. refer to table 22 for the groupings of the buffers. figure 15. first-order output buffer model table 20. parameters used in the specification of the first-order output buffer model parameter description dv/dt minimum and maximum value of the rate of change of the open circuit voltage source used in the output buffer model r o minimum and maximum value of the output impedance of the output buffer model c o minimum and maximum value of the capacitance of the output buffer model l p minimum and maximum value of the package inductance c p minimum and maximum value of the package capacitance table 21. buffer selection chart environment brdy# buffer selection typical stand alone component 1 eb2 loaded component 0 eb2a note: for correct buffer selection, the buschk# signal must be held inactive (high) at the falling edge of reset.
embedded pentium ? processor with voltage reduction technology 42 datasheet table 22. signal to buffer type signals type driver buffer type receiver buffer type clk i er0 a20m#, ahold, bf, boff#, brdy#, buschk#, eads#, ewbe#, flush#, hold, ignne#, init, intr, inv, ken#, na#, nmi, pen#, r/s#, reset, smi#, stpclk#, tck, tdi, tms, trst#, wb/wt# ier1 apchk#, be7#Cbe5#, bp3Cbp2, breq, ferr#, ierr#, pcd, pchk#, pm0/bp0, pm1/bp1, prdy, pwt, smiact#, tdo, u/o# oed1 a31Ca21, ap, be4#Cbe0#, cache#, d/c#, d63Cd0, dp8Cdp0, hlda, lock#, m/io#, scyc i/o eb1 eb1 a20Ca3, ads#, hitm#, w/r# i/o eb2/eb2a eb2/eb2a hit# i/o eb3 eb3 table 23. input, output and bidirectional buffer model parameters buffer type transition dv/dt (v/ns) r o (ohms) c p (pf) l p (nh) c o /c in (pf) min max min max min max min max min max er0 rising 3.0 5.0 4.0 7.2 0.8 1.2 (input) falling 3.0 5.0 4.0 7.2 0.8 1.2 er1 rising 1.1 6.1 4.7 15.3 0.8 1.2 (input) falling 1.1 6.1 4.7 15.3 0.8 1.2 ed1 rising 3/3.0 3.7/0.9 21.6 53.1 1.1 8.2 4.0 17.7 2.0 2.6 (output) falling 3/2.8 3.7/0.8 17.5 50.7 1.1 8.2 4.0 17.7 2.0 2.6 eb1 rising 3/3.0 3.7/0.9 21.6 53.1 1.3 8.7 4.0 18.7 2.0 2.6 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 1.3 8.7 4.0 18.7 2.0 2.6 eb2 rising 3/3.0 3.7/0.9 21.6 53.1 1.3 8.3 4.4 16.7 9.1 9.7 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 1.3 8.3 4.4 16.7 9.1 9.7 eb2a rising 3/2.4 3.7/0.9 10.1 22.4 1.3 8.3 4.4 16.7 9.1 9.7 (bidir) falling 3/2.4 3.7/0.9 9.0 21.2 1.3 8.3 4.4 16.7 9.1 9.7 eb3 rising 3/3.0 3.7/0.9 21.6 53.1 1.9 7.5 9.9 14.3 3.3 3.9 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 1.9 7.5 9.9 14.3 3.3 3.9 table 24. input buffer model parameters: d (diodes) symbol parameter d1 d2 is saturation current 1.4eC14 a 2.78eC16 a n emission coefficient 1.19 1.00 rs series resistance 6.5 ohms 6.5 ohms tt transit time 3 ns 6 ns vj pn potential 0.983 v 0.967 v cj0 zero bias pn capacitance 0.281 pf 0.365 pf m pn grading coefficient 0.385 0.376
embedded pentium ? processor with voltage reduction technology datasheet 43 4.4.2 signal quality specifications signals driven by the system into the embedded pentium processor with voltage reduction technology must meet signal quality specifications to guarantee that the components read data properly and to ensure that incoming signals do not affect the reliability of the component. there are two signal quality parameters: ringback and settling time. 4.4.2.1 ringback excessive ringback can contribute to long-term degradation of the reliability of the embedded pentium processor with voltage reduction technology, and can cause false signal detection. ringback is simulated at the input pin of a component using the input buffer model. ringback can be simulated with or without the diodes that are in the input buffer model. ringback is the absolute value of the maximum voltage at the receiving pin below v cc3 (or above v ss ) relative to the v cc3 (or v ss ) level after the signal has reached its maximum voltage level. the input diodes are assumed present. maximum ringback on inputs = 0.8 v (with diodes) if simulated without the input diodes, follow the maximum overshoot/undershoot specification. by meeting the overshoot/undershoot specification, the signal is guaranteed not to ringback excessively. if simulated with the diodes present in the input model, follow the maximum ringback specification. overshoot (undershoot) is the absolute value of the maximum voltage above v cc3 (below v ss ). the guideline assumes the absence of diodes on the input. ? the maximum overshoot/undershoot on the 3.3-v embedded pentium processor with voltage reduction technology inputs (not clk) = 1.4 v above v cc3 (without diodes) figure 16. overshoot/undershoot and ringback guidelines
embedded pentium ? processor with voltage reduction technology 44 datasheet 4.4.2.2 settling time the settling time is defined as the time required at the receiver for the signal to settle to within 10 percent of v cc3 or v ss . settling time is also the maximum time allowed for a signal to reach within 10 percent of its final value. most available simulation tools are unable to simulate settling time so that it accurately reflects silicon measurements. on a physical board, second-order effects and other effects can dampen the signal at the receiver. because of all these concerns, settling time is a recommendation or a tool for layout tuning and not a specification. settling time is simulated at the slow corner, to make sure that there is no impact on the flight times of the signals if the waveform has not settled. settling time may be simulated with the diodes included or excluded from the input buffer model. if diodes are included, the settling time recommendation will be easier to meet. although simulated settling time has not shown good correlation with physical, measured settling time, settling time simulations can still be used as a tool to tune layouts. use the following procedure to verify board simulation and tuning with concerns for settling time. 1. simulate settling time at the slow corner for a particular signal. 2. if settling time violations occur, simulate signal trace with dc diodes in place at the receiver pin. the dc diode behaves almost identically to the actual (non-linear) diode on the part as long as excessive overshoot does not occur. 3. if settling time violations still occur, simulate flight times for five consecutive cycles for that particular signal. 4. if flight time values are consistent over the five simulations, settling time should not be a concern. if however, flight times are not consistent over the five simulations, tuning of the layout is required. 5. note that, for signals that are allocated two cycles for flight time, the recommended settling time is doubled. a typical design method would include a settling time that ensures that a signal is within 10 percent of v cc3 or v ss for at least 2.5 ns prior to the end of the clk period. figure 17. settling time

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